To increase an operating speed, a synchronous memory device has been introduced which can operate in synchronization with a clock. An early type of synchronous memory device is a single data rate (SDR) synchronous memory device which inputs/outputs one data through a single data pin in one clock cycle in synchronization with a rising edge of a clock. However, the SDR synchronous memory device could not sufficiently meet high-speed requirements demanded by the systems. A double data rate (DDR) synchronous memory device, which processes two data in one clock cycle, was then introduced for higher speed operation than a SDR device.
A DDR synchronous memory device successively inputs/outputs two data through each data input/output pin in synchronization with rising and falling edges of an external clock. Without increasing the frequency of a clock, a DDR synchronous memory device can implement at least two times the bandwidth of a conventional SDR synchronous memory device. Hence, a DDR synchronous memory device can perform improved high-speed operations.
For even higher data transfer speeds in a DDR synchronous memory device, several additional concepts were introduced. In the DDR-II synchronous memory specification proposed in the Joint Electron Device Engineering Council (JEDEC), also called the global semiconductor standard organization or the international semiconductor standard council, an Off Chip Driver (OCD) calibration control concept was introduced, according to which the impedance of an OCD configured to output data in the DDR synchronous memory device can be calibrated.
The OCD calibration control is to calibrate the impedance of the OCD to an optimum level in a current system. Thus, to meet the DDR-II synchronous memory specification of the JEDEC, the function of calibrating the impedance of the OCD would be needed additionally.
The OCD calibration control operation proposed in the JEDEC includes an operation of measuring the impedance of an OCD and an operation of calibrating the impedance of an OCD suitably for the current system. Also, since an OCD includes a pull-up driver and a pull-down driver, the operation of measuring the impedance of an OCD is performed in two modes: a Drive1 mode in which the impedance of the pull-up driver outputting high-level data is measured; and a Drive0 mode in which the impedance of the pull-down driver outputting low-level data is measured.
Meanwhile, an On Die Termination (ODT) is a device designed to transfer a data signal to a next chip without impedance mismatching by adjusting a resistance of an output terminal when a memory device is integrated into a board.
FIG. 1 shows a conventional data output impedance control circuit in a block diagram.
As illustrated in FIG. 1, the conventional data output impedance control circuit includes an OCD control unit 100 and a plurality of OCDs 101 to 132. The OCD control unit 100 is configured to receive control codes CON<1:4> when an adjustment mode signal ADJ_MODE is at a logic high level, and generate pull-up signals PU<1:6> and pull-down signals PD<1:6>. The OCDs 101 to 132 are configured to receive the pull-up signals PU<1:6> and the pull-down signals PD<1:6> and output data whose impedance is calibrated.
In the conventional data output impedance control circuit having the above-described configuration, since the pull-up signals PU<1:6> and the pull-down signals PD<1:6> are applied to the OCDs 101 to 132 in a batch, the impedances of the OCDs 101 to 132 are equally calibrated.